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| Ordering number : ENA0919 LV8095LQ Overview Bi-CMOS IC For VCMs Constant-current Driver IC The LV8095LQ is a constant current driver IC for voice coil motors. It supports I2C control and integrates a digital/analog converter (DAC). Its ultraminiature package makes the IC ideal for constant-current driving the voice coil motors (AF and ZM) used in a wide variety of portable equipment including camera cell-phones. Features * Constant current driver for voice coil motors. * Constant current control enabled by DAC (8 bits). * Wide operating voltage range (2.5 to 5.5V). * I2C bus control supported. * No external capacitors needed (capacitor-less). * Ultraminiature package (USLP8 : 2.0x1.3x0.56mm) for easy soldering. * Built-in thermal protection circuit. * Built-in voltage drop protection circuit. Specifications Absolute Maximum Ratings at Ta = 25C Parameter Maximum supply voltage Maximum VDD voltage Output voltage Input voltage GND pin source current Allowable power dissipation Operating temperature Storage temperature Symbol VCC max VDD max VOUT max VIN max IGND Pd max Topr Tstg *Mounted on a specified board. OUT1 SCL, SDA, PD Conditions Ratings -0.3 to +5.5 -0.3 to +5.5 -0.3 to +6.0 -0.3 to +5.5 200 650 -30 to +85 -40 to +150 Unit V V V V mA mW C C * Specified board : 50mmx40mmx0.8mm, 4-layer glass epoxy circuit board. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. O3107 MS PC 20070827-S00002 No.A0919-1/8 LV8095LQ Allowable Operating Conditions at Ta = 25C Parameter Supply voltage VDD voltage Maximum preset output current High-level input voltage Low-level input voltage Symbol VCC VDD IO VIH VIL Applied to SCL, SDA, and PD pins Conditions Ratings 2.5 to 5.0 1.3 to 5.0 200 0.8xVDD to VDD -0.3 to 0.2xVDD Unit V V mA V V Electrical Characteristics Ta = 25C, VCC = 2.8V, VDD = 2.8V Parameter Supply current Symbol ICCO ICC1 Input current Output saturation voltage IIN Vsat1 PD = 0V PD = 2.8V VIN = 2.8V, VENA = 2.8V SW : ON, SW : b, Full code setting, IOUT = 50mA Vsat2 SW : ON, SW : b, Full code setting, IOUT = 100mA DAC block Resolution Relative accuracy Differential linearity Full code current Error code current 0 Spark killer diode Reverse current Forward voltage IS (leak) VSF IOUT = 200mA * 1 1.3 A V INL DNL Ifull Izero RF = 1, SW1 : OFF, SW2 : a RF = 1, SW1 : OFF, SW2 : a RF = 1, SW1 : OFF, SW2 : a RF = 1, SW1 : OFF, SW2 : a RF = 1, SW1 : OFF, SW2 : a 95 100 1 8 1 1 105 4 bits LSB LSB mA mA 0.20 0.4 V -1 Conditions min Ratings typ 0.1 0.5 0 0.10 max 1 3 1 0.18 A mA A V Unit *1 : Design guaranteed value (no measurement is performed) Package Dimensions unit : mm (typ) 3348 0.8 Pd max -- Ta Specified board : 50.0x40.0x0.8mm3 4-layer glass epoxy (2S2P) TOP VIEW 2.0 SIDE VIEW BOTTOM VIEW (0.18) 8 Allowable power dissipation, Pd max - W 0.7 0.65 0.6 0.5 0.4 1.3 (0.65) 0.14 2 0.25 0.5 1 (0.25) 0.34 0.3 0.2 0.1 0 - 30 - 20 0.0NOM 0.6MAX SIDE VIEW 0.3 1 2 0 20 40 60 80 100 Ambient temperature, Ta - C SANYO : USLP8(1.3X2.0) No.A0919-2/8 LV8095LQ Pin Assignment USLP8 (Top View) PD 8 SCL 7 SDA 6 VDD 5 Pin No. 1 2 3 4 5 6 7 8 Pin Name GND RFG OUT VCC VDD SDA SCL PD Ground Current sensing resistor connection Output pin Analog system power supply Logic system power supply *1 I2C SDA input I2C SCL input Power-down & reset *2 Pin Description 1 GND 2 RFG 3 OUT 4 VCC *1 : The voltage applied to the VDD pin must be set to the same level as those of the SDA, SCL and PD input high-level voltages. *2 : Setting the PD pin to low level powers down and resets the IC. Set this pin temporarily to low level, then to high level after power-on, and keep it to high level (same voltage level as VDD) during normal operation. Block Diagram VCC 0.1F Reference voltage Voltage drop protection & thermal protection VCM SDA C P U SCL I2C IF I2C DECODE DAC 8 bits current setting VDD + - OUT PD GND RF 1 RFG Wiring resistance (thick line) around the RF is added to the resistance of RF as an error. It must be kept as small as possible. Formula for calculating constant current : IOUT = 0.1 / RF If, for instance, IOUT is to be set to 100mA max : RF = 0.1 / (100mA) RF = 1 Notes on use * Determine the preset current value using the resistor between RFG and GND according to the formula above. * The recommended RF value is 1. No.A0919-3/8 LV8095LQ Pin Description Pin No. 1 2 3 Pin Name GND RFG OUT Ground pin 2 : RFG Current detection resistor connection pin The current detection resistor (1) is connected between this pin and GND to detect the output current and perform constant current control. 3 : OUT Output pin This is an NMOS open drain output, and the voice coil motor is connected between this pin and the VCC pin for use. Description Equivalent Circuit VCC 3 2 1k 4 5 VCC VDD 4 : VCC Power supply input pin 5 : VDD This is separate from the VCC power supply pin for the SDA, SCL and PD logic input, and it is used while the same voltage as that for the high level of these logic input is applied to it. 6 SDA I2C serial data input pin Input high level : 0.8 x VDD or higher Input low level : 0.2 x VDD or lower VDD 6 1k GND 7 8 SCL PD 7 : SCL I2C serial clock input pin 8 : PD Power down and reset When low, power-down and reset is performed at the same time. This pin is held high for normal use. In normal operation, however, this pin must be set low temporarily and an initial reset must be applied after VCC starts up. Input high level : 0.8 x VDD or higher Input low level : 0.2 x VDD or lower VDD 7 8 1k GND No.A0919-4/8 LV8095LQ Serial Bus Communication Specifications I2C serial transfer timing conditions Standard mode twH SCL twL th2 SDA th1 ts2 ts1 ts3 th1 tbuf Start condition ton tof Resend start condition Stop condition Input waveform condition Standard mode Parameter SCL clock frequency Data setup time symbol fscl ts1 ts2 ts3 Data hold time th1 th2 Pulse width twL twH Input waveform conditions ton tof Bus free time tbuf SCL clock frequency Setup time of SCL with respect to the falling edge of SDA Setup time of SDA with respect to the rising edge of SCL Setup time of SCL with respect to the rising edge of SDA Hold time of SCL with respect to the rising edge of SDA Hold time of SDA with respect to the falling edge of SCL SCL low period pulse width SCL high period pulse width SCL, SDA (input) rising time SCL, SDA (input) falling time Interval between stop condition and start condition 4.7 Conditions min 0 4.7 250 4.0 4.0 0 4.7 4.0 1000 300 typ max 100 unit kHz s ns s s s s s ns ns s High-speed mode Parameter SCL clock frequency Data setup time Symbol fscl ts1 ts2 ts3 Data hold time th1 th2 Pulse width twL twH Input waveform conditions ton tof Bus free time tbuf SCL clock frequency Setup time of SCL with respect to the falling edge of SDA Setup time of SDA with respect to the rising edge of SCL Setup time of SCL with respect to the rising edge of SDA Hold time of SCL with respect to the rising edge of SDA Hold time of SDA with respect to the falling edge of SCL SCL low period pulse width SCL high period pulse width SCL, SDA (input) rising time SCL, SDA (input) falling time Interval between stop condition and start condition 1.3 Conditions min 0 0.6 100 0.6 0.6 0 1.3 0.6 300 300 typ max 400 unit kHz s ns s s s s s ns ns s No.A0919-5/8 LV8095LQ I2C bus transmission method Start and stop conditions The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a data transfer operation. SCL SDA ts2 th2 When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is started when SDA is changed from high to low while SCL and SDA are high. Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is high. Start condition Stop condition SCL SDA th1 ts3 Data transfer and acknowledgement response After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I2C bus, a unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave address and to the command (R/W) indicating the transfer direction of the subsequent data. However, this IC is provided with only a write mode for receiving the data. Every time 8 bits of data for each byte are transferred, the ACK signal is sent from the receiving end to the sending end. Immediately after the clock pulse of SCL bit 8 in the data transferred has fallen to low, SDA at the sending end is released, and SDA is set to low at the receiving end, causing the ACK signal to be sent. When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status, the receiving end releases SDA at the falling edge of the ninth SCL clock. Start M S B Slave address L S B W A C K M S B Data L S B A C K M S B Data L S B A C K Stop SCL 1st byte SDA (WRITE) A1 A2 A3 A4 A5 A6 A7 0 2nd byte PD X D7 D6 D5 D4 D3 D2 X : DON'T CARE 3ed byte D1 D0 X X X X X X No.A0919-6/8 LV8095LQ The standard data transfer to this device consists of three bytes : the slave address of the first byte and the data of the second and third bytes. The table below shows the format of the second and third bytes. 2nd byte Serial data bits Function SD7 PD SD6 x SD5 D7 SD4 D6 SD3 D5 SD2 D4 SD1 D3 SD0 D2 SD7 D1 SD6 D0 SD5 x 3rd byte SD4 x SD3 x SD2 x SD1 x SD0 x Slave address : 0110011(0) PD : Power-down D1-D7 : 8-bit data used to set output constant current ; MIN = 00000000, MAX = 11111111 D0-D7 setting method (output current design values assume an RF of 1) Current setting code 0 1 2 D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 1 D1 0 1 0 Output setting (LSB) 0 1 2 Output current (mA) (design value) 0 0.392 0.784 254 255 1 1 1 1 1 1 1 1 1 1 1 1 0 1 254 255 99.608 100 Specified Test Circuit A A A 1F 8 PD 7 SCL 6 SDA 5 VDD GND 1 RFG 2 OUT 3 VCC 4 A 1F SW2 b SW1 1 V a 15 A No.A0919-7/8 LV8095LQ SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of October, 2007. Specifications and information herein are subject to change without notice. PS No.A0919-8/8 |
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